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logic-rust.git
master
Rust project to solve Computer Circuit Design course work
Mora Unie Youer
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*
feat: better way to print chip count
HEAD
master
Mora Unie Youer
2025-05-04
1
-3
/
+7
*
feat: show grouped solution parameters
Mora Unie Youer
2025-05-04
1
-57
/
+84
*
feat: split K1533 chip series files into `regular` and `performant`
Mora Unie Youer
2025-05-04
2
-8
/
+72
*
feat: use larger gates if specific is not found
Mora Unie Youer
2025-05-02
1
-2
/
+10
*
fix: no panic if gate has no chip
Mora Unie Youer
2025-05-02
1
-91
/
+72
*
feat: D to JK trigger truth table conversion
Mora Unie Youer
2025-05-02
2
-0
/
+55
*
fix: improve minimization algorithm
Mora Unie Youer
2025-05-02
1
-5
/
+39
*
fix: improve full NAND/NOR solutions
Mora Unie Youer
2025-05-02
1
-2
/
+2
*
feat: calculation of input signal current
Mora Unie Youer
2025-04-28
1
-10
/
+118
*
feat: solution parameter calculation
Mora Unie Youer
2025-04-28
1
-65
/
+389
*
perf: minimization algorithm now a little faster
Mora Unie Youer
2025-04-28
1
-1
/
+4
*
fix: incorrect CNF result when no variables are used
Mora Unie Youer
2025-04-28
1
-2
/
+2
*
feat: read truth table from file
Mora Unie Youer
2025-04-27
3
-96
/
+137
*
feat: wired OR
Mora Unie Youer
2025-04-23
1
-2
/
+19
*
feat: transform cubes to logic
Mora Unie Youer
2025-04-23
1
-5
/
+181
*
feat: basic minimization algorithm
Mora Unie Youer
2025-04-20
3
-1
/
+290
*
feat: initial commit
Mora Unie Youer
2025-04-20
6
-0
/
+149