| Commit message (Expand) | Author | Files | Lines | |
|---|---|---|---|---|
| 2025-05-02 | feat: use larger gates if specific is not found |  Mora Unie Youer | 1 | -2/+10 |
| 2025-05-02 | fix: no panic if gate has no chip | Mora Unie Youer | 1 | -91/+72 |
| 2025-05-02 | feat: D to JK trigger truth table conversion | Mora Unie Youer | 2 | -0/+55 |
| 2025-05-02 | fix: improve minimization algorithm | Mora Unie Youer | 1 | -5/+39 |
| 2025-05-02 | fix: improve full NAND/NOR solutions | Mora Unie Youer | 1 | -2/+2 |
| 2025-04-28 | feat: calculation of input signal current | Mora Unie Youer | 1 | -10/+118 |
| 2025-04-28 | feat: solution parameter calculation | Mora Unie Youer | 1 | -65/+389 |
| 2025-04-28 | perf: minimization algorithm now a little faster | Mora Unie Youer | 1 | -1/+4 |
| 2025-04-28 | fix: incorrect CNF result when no variables are used | Mora Unie Youer | 1 | -2/+2 |
| 2025-04-27 | feat: read truth table from file | Mora Unie Youer | 3 | -96/+137 |
| 2025-04-23 | feat: wired OR | Mora Unie Youer | 1 | -2/+19 |
| 2025-04-23 | feat: transform cubes to logic | Mora Unie Youer | 1 | -5/+181 |
| 2025-04-20 | feat: basic minimization algorithm | Mora Unie Youer | 3 | -1/+290 |
 |
index : logic-rust.git | |
| Rust project to solve Computer Circuit Design course work | Mora Unie Youer |
| summaryrefslogtreecommitdiff |