From 2bb629d846c6060dc620c909aec79e5dd1ab1942 Mon Sep 17 00:00:00 2001
From: Mora Unie Youer <mora_unie_youer@riseup.net>
Date: Mon, 8 Dec 2025 14:01:09 +0300
Subject: feat: add `verible` for [System]Verilog files

---
 flake.nix | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'flake.nix')

diff --git a/flake.nix b/flake.nix
index 5319107..9f2e478 100644
--- a/flake.nix
+++ b/flake.nix
@@ -171,6 +171,11 @@
                 typescript-language-server
               ];
 
+              verilog = [
+                verible
+                verilator
+              ];
+
               debug = [
                 lldb
               ];
-- 
cgit v1.2.3-70-g09d2